Semiconductor memory devices can be classified as a volatile memory device or a non-volatile memory device according to the data storage method. A volatile memory device can lose stored data when power is no longer supplied to the device. In contrast, a non-volatile memory device has a feature capable of retaining data during a state where power is not supplied. A non-volatile memory device having such a feature, for example, a flash memory device, can be used in mobile communication terminals, memory cards, and the like.
A method using a floating gate as a storage layer constituting a unit cell can be employed as a technique for implementing the non-volatile memory device. However, the memory device with the floating gate can present disadvantages in that charges are stored in polycrystalline silicon such that the memory device can be affected by a small defect of a tunnel dielectric layer, thereby potentially degrading data retention characteristics. More specifically, the floating gate non-volatile memory device can have a structure in which a tunnel dielectric layer, a floating gate, a control gate dielectric layer, and a control gate are sequentially stacked on a channel region of a semiconductor substrate. The floating gate non-volatile memory device having such a structure may be programmed using a hot electron injection method or the Fowler-Nordheim (F-N) tunneling method. When electrons are injected into the floating gate through the programming process, a threshold voltage can be increased. When a voltage smaller than the increased threshold voltage is applied to the control gate, current may not flow in a programmed cell. This process allows the stored data to be read. However, in the floating gate non-volatile memory cell, a problem associated with electron retention may occur. That is, in order for the non-volatile memory cell to retain the programmed data, it is desirable that the floating gate retain the injected electrons. Additionally, when there are defects, such as pinholes in the tunnel dielectric layer, the electrons injected into the floating gate may exit via the defects. Further, since the floating gate is formed of a conductive layer such as polycrystalline silicon, high leakage current may be generated even by defects present in a part of the tunnel dielectric layer.
Recently, semiconductor memory devices including nanocrystals have been studied as a means for potentially solving problems associated with a memory device having a floating gate.
Semiconductor memory devices including nanocrystals are described in U.S. Pat. No. 6,090,666 to Ueda et al. entitled “Method for Fabricating Semiconductor Nanocrystal and Semiconductor Memory Device using the Semiconductor Nanocrystal.”
Ueda et al. provides that in semiconductor memory devices including nanocrystals, semiconductor nanocrystals are formed on a semiconductor substrate and are used as storage patterns. More specifically, the semiconductor nanocrystals are formed of a semiconductor material such as silicon (Si) or germanium (Ge) and are spaced apart from each other by a dielectric layer. During programming, electrons are injected into the nanocrystals, and since the nanocrystals are spaced apart from each other, the movement of the electrons can be limited between the nanocrystals. Accordingly, even though a defect occurs in a part of a tunnel dielectric layer, leakage current resulting from the defect may affect only nanocrystals near the defect. Therefore, the nanocrystalline structure is capable of improving the charge retention capability of the memory device. Further, the higher the density of the nanocrystals, the more likely the improvement of the charge retention capability. Consequently, nanocrystals of small size as well as a plurality of nanocrystals per unit area are desirable.
Currently, however, semiconductor nanocrystals may be formed by depositing a silicon layer or a germanium layer on a semiconductor substrate using a chemical vapor deposition (CVD) method followed by annealing the silicon layer or germanium layer at a high temperature. The size of the semiconductor nanocrystals formed varies with the thickness of the silicon layer or germanium layer. Consequently, in order to form semiconductor nanocrystals having a small size, it is desirable to implement a technique of forming the silicon layer or germanium layer having a decreased thickness. However, a technique using the chemical vapor deposition (CVD) method has at least the limitations related to the deposition of the silicon layer or the germanium layer to achieve a decreased thickness as well as the adjustment of the deposition degree. Semiconductor nanocrystals generally have a size of about 8 nm. Therefore, it is desirable to utilize a technique capable of forming the nanocrystals in a smaller size.
In attempts to discover other methods for substituting the semiconductor nanocrystals, methods using metal nanocrystals have been studied. A semiconductor memory device using the metal nanocrystals is described in “Metal nanocrystals memories,” Liu et al., IEEE transactions on electron devices, VOL. 49, NO. 9, September 2002.
Liu et al. suggests that metal layers, such as a tungsten layer, a gold (Au) layer, or a silver (Ag) layer, are deposited on a semiconductor substrate by a chemical vapor deposition (CVD) method and then are annealed at a high temperature to form the metal nanocrystals. However, in the technique of using the chemical vapor deposition (CVD) method, it can be problematic to control deposition time and temperature, and thus, the size and density of the formed metal nanocrystals may not be desirable.
Accordingly, there is a need for a technique for forming nanocrystals having a small and uniform size and proper density on a semiconductor substrate.